Low-swing LC Resonant Clock Distribution Networks Using Conditional Capturing Flip-Flop

The clock distribution network in digital integrated circuits distributes the clock signal which acts as a timing reference controlling data flow within the system. Since the clock signal has highest capacitance and operates at high frequencies, the clock distribution network consumes a large amount of total power in synchronous system. So, a new flip-flop is proposed in a low-swing resonant clocking scheme. This low-swing differential conditional capturing flip-flop operates with a low-swing sinusoidal clock through utilization of reduced clocking inverters. The functionality of low-swing differential conditional flip-flop can be tested and verified using H-spice tool. Resonant clocking enables the generation of clock signals with reduced power consumption.